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Rev 2; 8/04
CPU Supervisor with Nonvolatile Memory and Programmable I/O
General Description
The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile (NV) I/O pins. It is configured with an industry-standard I 2 CTM interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose I2C-to-parallel I/O expander with unlimited read/write capability. EEPROM registers allow the power-on value of the I/O pins to be adjusted to keep track of the system's state through power cycles, and the CPU supervisor's timer can be adjusted between 125ms and 1000ms to meet most any application need.
Features
Accurate 5%, 10%, or 15% 5V Power-Supply Monitoring Programmable Reset Timer Maintains Reset After VCC Returns to an In-Tolerance Condition Four Programmable, NV, Digital I/O Pins with Selectable Internal Pullup Resistor 64 Bytes of User EEPROM Reduces Need for Discrete Components I2C-Compatible Serial Interface 10-Pin SOP Package
DS4510
Applications
RAM-Based FPGA Bank Switching for Multiple Profiles Industrial Controls Cellular Telephones PC Peripherals PDAs
PART DS4510U-5 DS4510U-10 DS4510U-15 DS4510U-5/T&R DS4510U-10/T&R DS4510U-15/T&R
Ordering Information
VCC TRIP POINT 5% 10% 15% 5% 10% 15% PINPACKAGE -40C to +85C 10 SOP TEMP RANGE -40C to +85C 10 SOP -40C to +85C 10 SOP -40C to +85C 10 SOP -40C to +85C 10 SOP -40C to +85C 10 SOP
Pin Configuration
TOP VIEW
Typical Operating Circuit
2.7V TO 5.5V
4.7k
A0 1 SDA SCL VCC GND 2 3 4 5
10 RST 9 I/O0 I/O1 I/O2 I/O3
4.7k
4.7k A0
VCC
RST I/O0
RESET CONFIG0
VCC
DS4510
8 7 6
FROM SYSTEM CONTROLLER
SDA
DS4510
SCL
I/O1 I/O2
CONFIG1 FPGA CONFIG2 CONFIG3 GND
GND
I/O3
SOP
I2C is a registered trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc. or one of its Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided the system conforms to the I2C Standard Specifications as defined by Philips. ______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, SDA, and SCL Pins Relative to Ground.....................................-0.5V to +6.0V Voltage Range on A0, I/O0, I/O1, I/O2, I/O3 Relative to Ground ..............-0.5V to VCC + 0.5V, not to exceed +6.0V. Operating Temperature Range ...........................-40C to +85C EEPROM Programming Temperature .....................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature .......................................See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C)
PARAMETER Supply Voltage Input Logic 1 Input Logic 0 SYMBOL VCC VIH VIL (Notes 1) (Note 2) CONDITIONS MIN 2.7 0.7 x VCC -0.3 TYP MAX 5.5 VCC + 0.3 +0.3 x VCC UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 5.5V, TA = -40C to +85C.)
PARAMETER VCC Trip Point Standby Current Input Leakage SDA Low-Level Output Voltage I/OX Low-Level Output Voltage RST Pin Low-Level Output I/OX Pullup Resistors I/O Capacitance SYMBOL DS4510U-5 VCCTP ISTBY IL VOL VOLIOX VOLRST RP CI/O (Note 5) 3mA sink current 6mA sink current 4mA sink current 10mA sink current (Note 4) 4.0 5.0 DS4510U-10 DS4510U-15 VCC = 5.0V (Note 3) -1.0 CONDITIONS MIN 4.5 4.25 4.0 TYP 4.625 4.375 4.125 50 MAX 4.75 4.49 4.24 75 +1.0 0.4 0.6 0.4 0.4 6.5 10 A A V V V k pF UNITS V
2
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CPU Supervisor with Nonvolatile Memory and Programmable I/O
CPU SUPERVISOR AC ELECTRICAL CHARACTERISTICS (See Figure 1)
(VCC = 2.7V to 5.5V, TA = -40C to +85C.)
PARAMETER SYMBOL CONDITIONS TD1= 0, TD0 = 0 RST Active Time tRST TD1= 0, TD0 = 1 TD1= 1, TD0 = 0 TD1= 1, TD0 = 1 TD1= 0, TD0 = 0 VCC Detect to RST tRPU TD1= 0, TD0 = 1 TD1= 1, TD0 = 0 TD1= 1, TD0 = 1 VCC Fail to RST tRPD MIN 112 225 450 900 112 225 450 900 TYP 125 250 500 1000 125 250 500 1000 4 MAX 138 275 550 1100 138 275 550 1100 10 s ms ms UNITS
DS4510
AC ELECTRICAL CHARACTERISTICS (See Figure 5)
(VCC = 2.7V to 5.5V, TA = -40C to +85C, timing referenced to VIL(MAX) and VIH(MIN).)
PARAMETER SCL Clock Frequency Bus Free Time Between Stop and Start Conditions Hold Time (Repeated) Start Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time Start Setup time SDA and SCL Rise Time SDA and SCL Fall Time Stop Setup Time SDA and SCL Capacitive Loading EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW (Note 7) (Note 7) 10 (Note 7) (Note 7) CONDITIONS (Note 6) MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF ms
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CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = 2.7V to 5.5V, TA = 0C to +70C.)
PARAMETER Writes SYMBOL +70C (Note 5) CONDITIONS MIN 50,000 TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
All voltages referenced to ground. The DS4510 does not obstruct the SDA and SCL lines if VCC is switched off, as long as the voltages applied to these inputs do not violate their min and max input voltage levels. ISTBY specified with VCC equal to 5.0V, and control port-logic pins are driven to ground or VCC for the corresponding inactive state (SDA = SCL = VCC), does not include pullup resistor current. See Typical Operating Characteristics for the RST output voltage vs. supply voltage. This parameter is guaranteed by design. I2C interface timing shown for is for fast-mode (400kHz) operation. This device is also backward compatible with I 2C standard-mode timing. CB--total capacitance of one bus line in picofarads. EEPROM write time applies to all the EEPROM memory and SEEPROM memory when SEE = 0. The EEPROM write time begins at the occurrence of a stop condition.
Typical Operating Characteristics
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS4510 toc01
SUPPLY CURRENT vs. TEMPERATURE
DS4510 toc02
SUPPLY CURRENT vs. SCL FREQUENCY
DS4510 toc03
50 VCC (10%) TRIP POINT
60 50 SUPPLY CURRENT (A) 40 30 20 10 SDA = SCL = VCC 0
70 60 SUPPLY CURRENT (A) 50 40 30 20 10 0 SDA = VCC
SUPPLY CURRENT (A)
45
40
35
SDA = SCL = VCC I/O CONTROL BITS = 0 I/O PULLUPS DISABLED 3.0 3.5 4.0 4.5 5.0
30 SUPPLY VOLTAGE (V)
-40
-20
0
20
40
60
80
0
100
200
300
400
TEMPERATURE (C)
SCL FREQUENCY (kHz)
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CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510
Typical Operating Characteristics (continued)
(VCC = +5.0V, TA = +25C, unless otherwise noted.)
VCC TRIP POINT vs. TEMPERATURE
DS4510 toc04
RST OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
DS4510 toc05
I/O PULLUP RESISTANCE vs. TEMPERATURE
5.20 I/O PULLUP RESISTANCE (k) 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 4.75
DS4510 toc06
5.0 4.9 4.8 VCC TRIP POINT (V) 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
6.0 5.5 RESET TRIP VOLTAGE (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
5.25
5.6k PULLUP RESISTOR ON RST SDA = SCL = VCC
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
-40
-20
0
20
40
60
80
TEMPERATURE (C)
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME A0 SDA SCL VCC GND I/O3 I/O2 I/O1 I/O0 RST FUNCTION I2C Address Input. This input pin determines the chip address of the device. A0 = 0 sets the slave address to 1010000b, A0 = 1 sets the slave address to 1010001b. Serial Data Input/Output. Bidirectional I2C data pin. Serial Clock Input. I2C clock input. Power Input Ground Input/Output 3. I2C accessible bidirectional I/O pin. Input/Output 2. I2C accessible bidirectional I/O pin. Input/Output 1. I2C accessible bidirectional I/O pin. Input/Output 0. I2C accessible bidirectional I/O pin. Active-Low Reset Output. Open-drain CPU supervisor reset output.
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CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510
Functional Diagram
VCC SDA SCL A0 INTERNAL VOLTAGE REFERENCE PROGRAMMABLE RESET TIMER 2-WIRE INTERFACE RST
DS4510
VCC VCC GND
4x
VCC
EEPROM 64 BYTES USER MEMORY
4 BIDIRECTIONAL NONVOLATILE I/O LATCHES PULLUP ENABLE (F0h) I/OX CONTROL (F4h-F7h) I/O STATUS (F8h) RP 4 NV I/O PINS
Detailed Description
The DS4510 contains a CPU supervisor, four programmable I/O pins, and a 64-byte EEPROM memory. All functions are configurable or controllable through an industry-standard I2C-compatible bus. DS4510 NV registers that are likely to require frequent modification are implemented using SRAM-shadowed EEPROM (SEEPROM) memory. This memory is configurable to act as volatile SRAM or NV EEPROM by adjusting the SEE bit in the Config register. Configuring the SEEPROM as SRAM eliminates the EEPROM write time and allows infinite write cycles to these registers. Configuring the registers as EEPROM allows the application to change the power-on values that are recalled during power-up.
determines if the power-on reset level of the DS4510 is surpassed by VCC. The trip point bit determines if VCC is above VCCTP, and the reset status bit is set if RST is in its active state. Note: The RST pin is an open-drain output, therefore an external pullup resistor must be used to realize high logic levels.
Programmable NV Digital I/O Pins
Each programmable I/OX pin contains an input, opencollector output, and a selectable internal pullup resistor. The DS4510 stores changes to the I/O X pin in SEEPROM memory. Using the SEEPROM as SRAM is conducive to applications such as I/O expansion that generally require fast access times and frequent modification of the I/OX pin. Configuring the SEEPROM to behave as EEPROM allows the modification of the power-on state of the I/OX pin. During power-up the I/OX pins are high impedance until VCC exceeds 2.0V (typically), which is when the last value programmed is recalled from EEPROM. On power-down, the I/OX state is maintained until VCC drops below 1.9V (typically). The internal pullups for each I/OX pin are controlled by the pullup-enable register (F0h). Similarly, the individual I/OX control registers (F4h to F7h) adjust the pulldown
Programmable CPU Supervisor
The timeout period is adjusted by writing the reset delay register (SEEPROM). The delay for each setting is shown in the CPU Supervisor AC Electrical Characteristics. If the SEE bit is set, changes are written to SRAM. On power-up the last value written to the EEPROM is recalled. The I2C bus is also used to activate the RST by setting the SWRST bit in the Config register. This bit automatically returns to zero after the timeout period. The Config register also contains the ready, trip point, and reset status bits. The ready bit
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CPU Supervisor with Nonvolatile Memory and Programmable I/O
transistors. Read the I/O status register (F8h) to determine the logic levels present at the I/O pins.
DS4510
tR VCCTP (MIN) VCCTP tRPU VCCTP (MAX) VCCTP (MAX) VCCTP
tF VCCTP (MIN) tRPD
User Memory
Three types of memory are present in the DS4510 (EEPROM, SEEPROM, and SRAM). The main user memory is 64 bytes of EEPROM starting at address 00h. This memory is not SRAM shadowed, so all writes to these locations result in EEPROM write cycles regardless of the state of the SEE bit. Additional memory for storing application data includes 6 bytes of SRAM (FAh-FFh), and 2 bytes of SEEPROM (F2h, F3h). Refer to the register memory map (Figure 3) for register addresses and memory types. Figure 4 shows the bit names for the memory-mapped I/O bytes and their factory default values. The higher-order bits of the I/O registers that are not used, such as the four most significant bits of the pullup-enable byte (address F0h), can be used as additional memory. It is the responsibility of the application to ensure that writes to these bytes do not adversely affect bits controlling special functions of the DS4510.
VOH
VOL
Figure 1. CPU Supervisor Power-Up and Power-Down Timing
REGISTER ADDRESS (HEX)
MEMORY TYPE
F8 I/O STATUS
SRAM
REGISTER NAME
Figure 2. How to Read the Memory Map
00 USER BYTE 08 USER BYTE 10 USER BYTE 18 USER BYTE 20 USER BYTE 28 USER BYTE 30 USER BYTE 38 USER BYTE 40
EE 01 USER BYTE EE 09 USER BYTE EE 11 USER BYTE EE 19 USER BYTE EE 21 USER BYTE EE 29 USER BYTE EE 31 USER BYTE EE 39 USER BYTE 41
EE 02 User byte EE 0A USER BYTE EE 12 USER BYTE EE 1A USER BYTE EE 22 USER BYTE EE 2A USER BYTE EE 32 USER BYTE EE 3A USER BYTE 42
EE 03 USER BYTE EE 0B USER BYTE EE 13 USER BYTE EE 1B USER BYTE EE 23 USER BYTE EE 2B USER BYTE EE 33 USER BYTE EE 3B USER BYTE 43
EE 04 USER BYTE EE 0C USER BYTE EE 14 USER BYTE EE 1C USER BYTE EE 24 USER BYTE EE 2C USER BYTE EE 34 USER BYTE EE 3C USER BYTE 44 RESERVED
EE 05 USER BYTE EE 0D USER BYTE EE 15 USER BYTE EE 1D USER BYTE EE 25 USER BYTE EE 2D USER BYTE EE 35 USER BYTE EE 3D USER BYTE 45
EE 06 USER BYTE EE 0E USER BYTE EE 16 USER BYTE EE 1E USER BYTE EE 26 USER BYTE EE 2E USER BYTE EE 36 USER BYTE EE 3E USER BYTE 46
EE 07 USER BYTE EE 0F USER BYTE EE 17 USER BYTE EE 1F USER BYTE EE 27 USER BYTE EE 2F USER BYTE EE 37 USER BYTE EE 3F USER BYTE 47
EE EE EE EE EE EE EE EE
E8 F0 SEE PULLUP ENABLE F8 SRAM I/O STATUS
E9 EA SEE F2 F1 RESET DELAY USER BYTE F9 SRAM FA CONFIG USER BYTE
EB SEE F3 USER BYTE SRAM FB USER BYTE
EC SEE F4 SEE I/O3 CONTROL SRAM FC SRAM USER BYTE
ED F5 SEE I/O2 CONTROL FD SRAM USER BYTE
EE F6 SEE I/O1 CONTROL FE SRAM USER BYTE
EF F7 SEE I/O0 CONTROL FF SRAM USER BYTE
*ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3.
Figure 3. Register Memory Map
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CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510
REGISTER REGISTER LOCATION NAME (HEX) User EEPROM Reserved Pullup Enable RST Delay User SEE User SEE I/O3 Control I/O2 Control I/O1 Control I/O0 Control I/O Status Config User SRAM 00-3F 40-EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA-FF REGISTER BIT NAMES Bit 7 EE n/a SEE SEE SEE SEE SEE SEE SEE SEE 0 ready SRAM Bit 6 EE n/a SEE SEE SEE SEE SEE SEE SEE SEE 0 trip point SRAM Bit5 EE n/a SEE SEE SEE SEE SEE SEE SEE SEE 0 reset status SRAM Bit 4 EE n/a SEE SEE SEE SEE SEE SEE SEE SEE 0 SEE SRAM Bit 3 EE n/a I/O3 pullup SEE SEE SEE SEE SEE SEE SEE I/O3 Status SWRST SRAM Bit 2 EE n/a I/O2 pullup SEE SEE SEE SEE SEE SEE SEE I/O2 Status 0 SRAM Bit 1 EE n/a I/O1 pullup TD1 SEE SEE SEE SEE SEE SEE I/O1 Status 0 SRAM Bit 0 EE n/a I/O0 pullup TD0 SEE SEE I/O3 I/O2 I/O1 I/O0 I/O0 Status 0 SRAM FACTORY OR POWER-ON DEFAULT (BIN) 00000000 n/a 00000000 00000011 00000000 00000000 00000001 00000001 00000001 00000001 n/a XXX00000 00000000
Figure 4. Register Bit Names
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start, and stop conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning
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SDA from low to high while SCL remains high generates a stop condition. See the I2C Timing Diagram for applicable timing. Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See the I2C Timing Diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL (see Figure 5) plus the setup and hold-time requirements. Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup
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CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510
Table 1. Register Definitions
REGISTER LOCATION (HEX) 00 to 3F 40 to EF F0 F1 F2 to F3 F4 to F7 F8 F9 REGISTER NAME User EEPROM Reserved Pullup Enable RST Delay User SEEPROM I/OX Control I/O Status Config Bit Name ready Trip Point Reset Status SEE SWRST FA to FF User SRAM 64 bytes of EEPROM memory. These memory locations are reserved for future products. The four least significant bits of this register each enable/disable one of the internal pullup resistors. Set the bit to enable the pullup, clear it to disable the pullup. The two LSBs of this register (TD1 and TD0) select the reset delay (tRST) as shown in the CPU Supervisor AC Timing Characteristics. SRAM Shadowed EEPROM user byte. Clearing the LSB of the register enables the I/OX pulldown transistor; setting the bit disables the pulldown transistor. This register reflects the logic level of the I/OX pins. The upper four bits of this register always read zero. This register contains 5 bits that read and control the behavior of the part as follows: Bit Function Reads zero when VCC is above the DS4510's power-on reset voltage. Reads one when VCC below VCCTP. Reads one when the RST pin is active. When zero, writes to the SEEPROM registers behave like EEPROM. When one, writes to the SEEPROM registers behave like SRAM. Setting this bit activates the RST output. This bit automatically returns to zero during the RST active time. 6 bytes of SRAM memory FUNCTION
time (see Figure 5) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 5) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition above, and the master transmits an ACK using the bit-write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave Address and the R/W Bit: Each slave on the I2C bus responds to a slave addressing byte sent immediately following a start condition. The slave address byte contains the slave address and the R/W bit. The slave address (see Figure 6) is the most significant 7 bits and the R/W bit is the least significant bit. The DS4510's slave address is 101000A0 (binary), where A 0 is the value of the A 0 address pin. The
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CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510
SDA tBUF tLOW SCL tHD:STA STOP START tHD:DAT NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN) tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO tR tF
tHD:STA
tSP
Figure 5. I2C Timing Diagram
address pin allows for the DS4510 to respond to one of two slave addresses (1010000X, or 1010001X). If the R/W bit is zero, the master writes data to the slave. If the R/W is one, the master reads data from the slave. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte (R/W = 0).
I2C Communications
Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address (R/W= 0), write the memory address, write the byte of data and generate a stop condition. Remember the master must read the slave's acknowledgement during all byte write operations. Writing a Multiple Bytes to a Slave: To write multiple bytes to a slave the master generates a start condition, writes the slave address (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. The DS4510 can write 1 to 8 bytes (one page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory table, see Figure 3). Attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. Example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three "consecutive" addresses. The result would be addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. To prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. The master may then generate a new start con-
7-BIT SLAVE ADDRESS 10 1 0 0 0 A0 R/W
MOST SIGNIFICANT BIT
A0 PIN VALUE
DETERMINES READ OR WRITE
Figure 6. DS4510's Slave Address and the R/W Bit
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CPU Supervisor with Nonvolatile Memory and Programmable I/O
dition, write the slave address (R/W = 0), and the first memory address of the next page before continuing to write data. Acknowledge Polling: Any time an EEPROM page is written, the DS4510 requires the EEPROM write time (tW) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the DS4510 does not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeated addressing the DS4510, which allows the next page to be written as soon as the DS4510 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of tW to elapse before attempting to write again to the DS4510. EEPROM Write Cycles: When EEPROM writes occur, the DS4510 writes the whole EEPROM memory page even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page one byte at a time wears the EEPROM out eight times faster than writing the entire page at once. The DS4510's EEPROM memory is guaranteed to handle 50,000 write cycles at +70C. Writing to SEEPROM memory with SEE = 1 does not count as an EEPROM write cycle when evaluating the EEPROM's estimated lifetime. Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave the master generates a start condition, writes the slave address with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a start condition, writes the slave address (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. See Figure 7 for a read example using the repeated start condition dummy write cycle. Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it NACKs to indicate the end of the transfer and generates a stop condition. This can be done with or without modifying the address counter's location before the read cycle. The DS4510 does not wrap on page boundaries during read operations, but the counter rolls from its upper-most memory address FFh to 00h if the last memory location is read during the read transaction. Example: The entire memory contents of the DS4510 can be read with a single transfer starting at address F0h that reads 80 bytes of data. Addresses F0h to FFh are read sequentially, the address counter rolls to 00h, and then addresses 00h to 3Fh can be read sequentially. This allows the entire memory contents to be read in a single operation without reading the undefined contents of the reserved area of the memory.
DS4510
Application Information
Advantages of Using the SEE Bit to Disable EEPROM Writes
The SEE bit allows EEPROM writes to be disabled for the SRAM-shadowed EEPROM bytes, allowing the SRAM of SEE registers to change without writing the EEPROM to the same value. This prevents write operations from changing the power-on value of the I/O pins, reduces the number of EEPROM write cycles, and speeds up I/O operations because the DS4510 does not require an internally timed EEPROM write cycle to complete the operation.
Power-Supply Decoupling
To achieve the best results when using the DS4510, decouple the power supply with a 0.01F or a 0.1F capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins of the DS4510 to minimize lead inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS4510 that requires a pullup resistor to realize high logic levels. Because the DS4510 does not utilize clock cycle stretching, a master using either an open-collector output with a pullup resistor or a normal output driver can be utilized for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC Electrical Characteristics are within specification.
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11
CPU Supervisor with Nonvolatile Memory and Programmable I/O DS4510
COMMUNICATIONS KEY S START A ACK NOT ACK XX XX WHITE BOXES INDICATED THE MASTER IS CONTROLLING SDA SHADED BOXES INDICATED THE SLAVE IS CONTROLLING SDA XX XX 8-BITS ADDRESS OR DATA NOTES: 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT.
P
STOP REPEATED START
N
Sr
WRITE A SINGLE BYTE S 1 01 00 0 A0 0 A MEMORY ADDRESS A DATA A P
WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION S 1 01 00 0 A0 0 A MEMORY ADDRESS A DATA A DATA A P
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER S 1 01 00 0 A0 0 A MEMORY ADDRESS A Sr 10 100 0 A0 1 A DATA N P
READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER S 1 01 00 0 A0 0 A MEMORY ADDRESS A Sr 10 100 0A 0 1 A DATA A
DATA
A
DATA
A
DATA
N
P
Figure 7. I2C Communications Examples
Chip Topology
TRANSISTOR COUNT: 16559 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.

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